Automated Synthesis of Bus Architectures for Systems with Throughput Constraints ∗

As System-on-Chip (SoC) designs become more complex, it becomes increasingly harder to design communication architectures which satisfy designer constraints. Manually traversing the vast communication design space for constraint-driven synthesis is not feasible anymore. In this report we propose an approach that automates the synthesis of bus-based communication architectures for systems characterized by (possibly several) throughput constraints. Our approach accurately and effectively prunes the large communication design space to synthesize a feasible low-cost bus architecture which satisfies all throughput constraints. We present a case study of a broadband SoC subsystem, for which we were able to synthesize a bus architecture in a matter of hours, instead of days or even weeks it would have taken for a manual effort. ∗ This work was partially supported by grants from Conexant Systems Inc. and UC Micro (03-029)